Senior Wi-Fi SoC System Power Management Engineer

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We are seeking a senior Wi-Fi SoC System Power Management Architect to join our SoC Design System Group. In this role, you will drive the power and clocking architecture for next-generation Wi-Fi SoCs specifically tailored for the ultra-low-power IoT market. You will work within a highly collaborative environment where excellent teamwork across hardware, software, and RF domains is critical to delivering industry-leading power-performance-area (PPA) efficiency.

Core Responsibilities

• Expert Low-Power Optimization: Drive ultra-low-power architectural definitions, optimizing active, idle, and deep-sleep modes to meet the stringent battery-life constraints of the IoT market.
• Wi-Fi Protocol Alignment: Apply deep knowledge of Wi-Fi standards to align the power architecture with protocol states, optimizing duty cycles, beacon listening, wake-up radio (WUR) features, and low-power network association.
• Power & Clock Architecture Definition: Define and partition power rails, voltage domains, and multi-domain clock distribution networks. Establish unified clocking strategies across the SoC to minimize jitter and phase noise.
• PLL & Clock Subsystem Design: Architect and specify Phase-Locked Loops (PLLs, including fractional-N and ADPLL variants) and Delay-Locked Loops (DLLs). Define lock-time profiles, fast-wake behaviors, and fallback clock-switching mechanisms to optimize power state transitions.
• Domain Partitioning & Control: Design the HW required to govern power and clock gating. Oversee Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) strategies across mixed-signal boundaries.
• Cross-Functional HW/SW Co-Design: Partner closely with firmware and driver teams to orchestrate aggressive dynamic voltage and frequency scaling (DVFS), sleep timers, and protocol-specific power-saving mechanisms tied directly to PLL settling constraints.
• Post-Silicon Validation & Lab Testing: Lead post-silicon validation, power measurement, and clock integrity testing on real hardware. Hands-on lab work to measure, debug and correlate empirical data with pre-silicon power models and debug power or clock anomalies.
• Collaborative Team Leadership: Foster a culture of excellent teamwork and open communication, driving alignment across RF, analog, digital design, physical implementation, firmware, and validation teams.

Key Requirements & Qualifications

• Education: Degree in Electrical Engineering
• Low-Power IoT Expertise: Proven track record in expert-level low-power optimizations for wireless/Wi-Fi SoCs or mixed-signal ICs, with a clear understanding of IoT market dynamics (e.g., maximizing battery life, optimizing leakage, fast wake-up states).
• Wi-Fi Standards Expertise: Deep knowledge of Wi-Fi IEEE 802.11 standards (e.g., 802.11b/g/n/ax/be/ba) with an understanding of how MAC/PHY layer features impact system power states and overall energy consumption.
• Teamwork & Communication: Excellent teamwork skills with a demonstrated ability to collaborate, influence, and align goals across multidisciplinary, global engineering teams.
• PLL & Clock Expertise: Proven track record in the architectural definition and system integration of analog/digital PLL subsystems. Deep understanding of clock architectures, frequency synthesis, jitter budgets, and clock-gating methodologies.
• Lab Skills: Hands-on experience with post-silicon validation, power measurement instrumentation (e.g., oscilloscopes, source measure units), and automated test setups.
• Advantage: A deep understanding of the RF and analog chain (such as LNAs, PAs, PLLs, and data converters) is a major advantage.