Senior CPU RTL Design Engineer, Subsystem

Google

New Taipei City, TaiwanYesterday

Key details

Location: New Taipei City, Taiwan
Work style: Onsite
Level: Senior
Experience: 8–11 yrs
Function: Hardware, mechanical & civil engineering
Focus area: other
Posted: Yesterday

Skills

androiddesign for testphysical designrtl designrtossystem on chip

About the role

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including quality assurance and integration into target System on a chip (SoC). You will collaborate with members of architecture, software, verification, power, DFT, physical design, etc., to specify and coordinate delivery of high quality Register-Transfer Level (RTL) into SoC. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Participate in developing CPU or AI accelerator design and deliveries into SoC.
Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Deliver designs that meet PPA and functional goals with modern techniques, interpret the techniques into design constructs, and languages in order to participate in SoC integration effort.
Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).

Preferred qualifications:

Experience with ARM Instruction set architecture.
Experience with SOC design, architect and integration.
Experience with real-time operating systems (e.g. Android).
Experience with DFT, sensor integration, debug architecture.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).

In most instances, this position requires in-person interviews as part of the hiring process.

Google welcomes people with disabilities.

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